1. Field of the Invention
The present invention relates to an electrical interconnection and a method of forming the electrical interconnection, and to an image sensor having the electrical interconnection and a method of manufacturing the image sensor. More particularly, the present invention relates to an electrical interconnection of copper and a method of forming the electrical interconnection, and to a complementary metal oxide semiconductor (CMOS) image sensor having the electrical interconnection of copper and a method of manufacturing the CMOS image sensor.
2. Description of the Related Art
The availability and use of information media and equipment for processing information media, e.g., computers, has been steadily increasing. Components using semiconductor technology are under pressure to keep pace with these developments. These developments require semiconductor devices that operate at a high speed and having a large storing capacitance. As a result, semiconductor technology is continuously striving to improve integration, reliability and response speed of semiconductor devices.
Generally, a semiconductor device includes a great number of transistors, resistors and capacitors. A semiconductor device needs interconnections for electrically connecting the transistors, the resistors and the capacitors. Electrical interconnections transmit an electrical signal, and numerous such electrical interconnections are required for a semiconductor device. Thus, electrical interconnections need to have low electrical resistance, low cost and high reliability. As semiconductor devices become more highly integrated, the width and thickness of the electrical interconnections and the size of a contact hole through which the electrical interconnections extend are correspondingly reduced. Therefore, a design rule of a semiconductor device is also reduced accordingly, as a pattern size shrinks. The resulting reduced feature size increases the difficulty of forming electrical interconnections on a semiconductor substrate.
The increased difficulty in forming wirings imposes strict requisites on a metal layer forming electrical interconnections on the substrate. To meet these needs, metal layers have been coated to be a multi-layer structure so as to increase the degree of integration of the semiconductor device. In general, aluminum (Al) or tungsten (W) has been widely used for coating the metal layer. However, aluminum and tungsten have high specific resistances of 2.8×10−8 Ωm and 5.5×10−8 Ωm, respectively, and thus are not suitable for a multi-layer structure. Recently, copper (Cu), which has low specific resistance and a good electro-migration characteristic, has replaced aluminum and tungsten in forming a metal multi-layer.
However, Cu has a high rate of diffusion with respect to silicon or silicon oxide. Therefore, a barrier metal layer and a diffusion barrier layer are required for preventing diffusion of Cu into the substrate. The barrier metal layer is coated on side and lower surfaces of a copper pattern, and the diffusion barrier layer is coated on an upper surface of the copper pattern.
A reactive ion etching (RIE) process is difficult to perform on copper, so a damascene process is used to form a copper pattern. In the damascene process for forming the copper pattern, the diffusion barrier layer functions as a stop layer of an etching process. The diffusion barrier layer usually includes silicon nitride, which has a high etching selectivity relative to an insulation interlayer and is good at preventing Cu diffusion. In general, silicon nitride is deposited to a thickness of about 300 Å to 1000 Å in order to prevent the Cu from diffusing and to ensure that the copper layer properly functions. However, silicon nitride has a dielectric constant of about eight. This high dielectric constant increases a parasitic capacitance between wirings, thereby reducing a response time of the signal.
Recently, Cu wiring has been used as wiring in optoelectronic devices, e.g., a complementary metal oxide semiconductor (CMOS) image sensor (hereinafter, “CIS”).
A CIS transforms optical images into electrical signals utilizing the CMOS technology. A recent dramatic increase in demand for digital image devices, e.g., in digital still cameras and cameras incorporated into mobile phones, door phones and so on, has given rise to an enormous demand for CISs. Furthermore, CISs have been improved to have higher performance, as the variety of CIS applied products increases. For example, a CIS is currently manufactured under a design rule of 0.18 μm, and is expected to be manufactured under a design rule of 0.13 μm in the near future.
When a CIS is manufactured under a design rule of 0.13 μm or below, using aluminum to form electrical interconnections of a CIS will be difficult. Thus, copper will be used to form electrical interconnections of a CIS manufactured under a design rule of 0.13 μm or below. As noted above, when a copper pattern is formed by the damascene process, a diffusion barrier layer of silicon nitride is required for stopping an etching process and preventing diffusion of copper, as described above. However, silicon nitride is highly absorptive of light. Thus, a certain amount of light is absorbed into the diffusion barrier layer, thereby preventing light from reaching a detector of the image sensor. Therefore, the silicon nitride diffusion barrier layer is a critical weak point of a CIS having a photodetector for detecting external light.
Table 1 shows an experimental light absorption percentage of silicon nitride according to a thickness of the silicon nitride layer and wavelengths of light at 400 (nm) and 500 (nm).
TABLE 1Wavelength 400 (nm)wavelength 500 (nm)thickness (nm)light absorptionlight absorption40 8% 3%8016% 6%12023% 9%16030%12%20036%15%24041%18%28046%20%32051%23%36055%25%
A CIS including copper wirings requires at least a silicon nitride layer as the diffusion barrier layer on each wiring layer. For example, when the diffusion barrier layer is formed of six-layers of silicon nitride, each having a thickness of about 500 Å, the overall thickness of the diffusion barrier layer is about 3,000 Å. As can be seen in Table 1, as much as about 48% of external light incident on the silicon nitride diffusion barrier layer will be absorbed. That is, almost half of the supplied light is absorbed into the diffusion barrier layer. Such absorbed light will not reach the photodetector, which is at a lower portion of the CIS, thereby causing an operation failure.